Vertical memory devices and methods of manufacturing the same

ABSTRACT

Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 USC §119 to Korean PatentApplication No. 10-2013-0145724, filed on Nov. 27, 2013 in the KoreanIntellectual Property Office (KIPO), the contents of which are herebyincorporated herein by reference in their entirety.

BACKGROUND

1. Field

Example embodiments relate to vertical memory devices and methods ofmanufacturing the same. More particularly, example embodiments relate tovertical memory devices having a vertical channel and methods ofmanufacturing the same.

2. Description of the Related Art

In methods of manufacturing vertical memory devices, an insulation layerand a sacrificial layer may be alternately and repeatedly formed on asubstrate. Holes may be formed though the insulation layers and thesacrificial layers. Channels may be formed to fill the holes. Openingsmay be formed through the insulation layers and the sacrificial layers.The sacrificial layers exposed by the openings may be removed to formgaps exposing the channels. ONO layers and gate structures includinggate electrodes may be formed to fill the gaps.

In order to increase the degree of integration, more channels may bedisposed in a predetermined area. When the channels may be disposedadjacent to each other, voids may occur during a process for forming agate electrode layer, and a space for receiving bit lines may beinsufficient.

SUMMARY

Nonvolatile memory devices according to some embodiments of theinvention can include at least four cylindrical-shaped channel regions,which extend vertically from portions of a substrate located atrespective vertices of at least one rhomboid when viewed in a verticaldirection relative to a surface of the substrate. A charge storage layer(e.g., ONO layer) is provided on an outer sidewall of each of thecylindrical-shaped channel regions. In addition, to achieve a highdegree of integration, a plurality of vertically-stacked gate electrodesare provided, which extend adjacent each of the cylindrical-shapedchannel regions.

According to additional embodiments of the invention, the memory deviceincludes at least seven cylindrical-shaped channel regions, which arepositioned at high density at respective vertices of two rhomboids thatshare a common vertex when viewed in a vertical direction relative tothe surface of the substrate. According to still further embodiments ofthe invention, the memory device includes five cylindrical-shapedchannel regions, which are positioned at respective vertices of tworhomboids that share three common vertices when viewed in a verticaldirection relative to the surface of the substrate. According to furtherembodiments of the invention, the memory device includes sevencylindrical-shaped channel regions positioned at respective vertices offour rhomboids that share a common vertex when viewed in a verticaldirection relative to the surface of the substrate. In particular, oneof the seven cylindrical-shaped channel regions may be located at avertex that is shared by each of the four rhomboids.

According to additional embodiments, there is provided a vertical memorydevice. The vertical memory device includes a plurality of channelarrays, a charge storage layer structure, and a plurality of gateelectrodes. The plurality of channel arrays includes a plurality ofchannels in a first region on a substrate. Each of the channels extendsin a first direction substantially perpendicular to a top surface of thesubstrate. The charge storage layer structure includes a tunnelinsulation layer pattern, a charge storage layer pattern and a blockinglayer pattern which are sequentially stacked on a sidewall of eachchannel in a second direction substantially parallel to the top surfaceof the substrate. The plurality of gate electrodes are arranged on asidewall of the charge storage layer structure, and spaced apart fromeach other in the first direction. Each of the channel array includes afirst channel column including a plurality of first channels disposed ata central portion of the first region with respect to a third directionsubstantially perpendicular to the first direction and the seconddirection, a second channel column including a plurality of secondchannels disposed at a outer portion of the first region, and a thirdchannel column including a plurality of third channels disposed at theouter portion of the first region. The second channels are spaced apartfrom respective first channels in a fourth direction oblique to thethird direction, The third channels are spaced apart from respectivesecond channels in the second direction.

In example embodiments, the first channels, the second channels and thethird channels may be arranged in a zigzag pattern with respect to thethird direction.

In example embodiments, the vertical memory device may further include afirst conductive pattern electrically connecting a second channel of onechannel array with a third channel of another channel array, and asecond conductive pattern electrically connecting a third channel of onechannel array with a second channel of the other channel array.

In example embodiments, the plurality of channel arrays may include afirst channel array, a second channel array spaced apart from the firstchannel array in a direction opposed to the second direction, and athird channel array spaced apart from the first channel array in thesecond direction.

In example embodiments, the first conductive pattern may electricallyconnect the second channel of the first channel array with the thirdchannel of the second channel array, and the second conductive patternmay electrically connect the third channel of the first channel arraywith the second channel of the third channel array.

In example embodiments, a plurality of first conductive patterns may bearranged in the third direction, and a plurality of second conductivepatterns may be arranged in the third direction.

In example embodiments, a central portion of the first conductivepattern may be curved in the third direction, and a central portion ofthe second conductive pattern may be curved in a direction opposed tothe third direction.

In example embodiments, the central portion of the first conductivepattern may not overlap the central portion of the second conductivepattern with respect to the second direction.

In example embodiments, the vertical memory device may further include afirst bit lines, a second bit lines and a third bit lines electricallyconnected to respective channels.

In example embodiments, the first bit lines may be electricallyconnected to the first channels, the second bit lines may beelectrically connected to the second channels or the third channelsthrough the first conductive patterns, and the third bit lines may beelectrically connected to the second channels or the third channelsthrough the second conductive patterns.

In example embodiments, the first bit lines may overlap central portionsof the first channels with respect to the first direction, the secondbit lines may overlap central portions of the first conductive patternswith respect to the first direction, and the third bit lines may overlapcentral portions of the second conductive patterns with respect to thefirst direction.

In example embodiments, the first bit lines, the second bit lines andthe third bit lines may extend in the second direction. The first bitlines, the second bit lines and the third bit lines may be arrangedalternately and repeatedly in the third direction.

In example embodiments, the first bit lines, the second bit lines andthe third bit lines may extend in a direction oblique to the seconddirection, and the first bit lines, the second bit lines and the thirdbit lines may be arranged alternately and repeatedly in the thirddirection.

According to example embodiments, there is provided a method ofmanufacturing a vertical memory device. In the method, a sacrificiallayer and an insulation layer are formed on a substrate alternately andrepeatedly. A plurality of holes is formed through the sacrificiallayers and the insulation layers to expose a top surface of thesubstrate. The plurality of holes constitutes a hole array. A blockinglayer pattern, a charge storage layer pattern, a tunnel insulation layerpattern and a channel are formed on a sidewall of each hole,sequentially. A plurality of gaps is formed by removing the sacrificiallayers to expose a sidewall of each blocking layer pattern. A gateelectrode is formed to fill each gap. Each of hole arrays includes afirst hole column including a plurality of first holes disposed at acentral portion of the first region with respect to a third directionsubstantially perpendicular to the first direction and the seconddirection, a second hole column including a plurality of second holesdisposed at a outer portion of the first region, and a third hole columnincluding a plurality of third holes disposed at the outer portion ofthe first region. The second holes are spaced apart from respectivefirst holes in a fourth direction oblique to the third direction. Thethird holes are spaced apart from respective second holes in the seconddirection.

In example embodiments, a first conductive pattern is formed toelectrically connect a channel in a second hole of one hole array with achannel in a third hole of another hole array. A second conductivepattern is formed to electrically connect a channel in a third hole ofone hole array with a channel in a second hole of the other hole array.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be more clearly understood from the followingdetailed description taken in conjunction with the accompanyingdrawings. FIGS. 1 to 21 represent non-limiting, example embodiments asdescribed herein.

FIGS. 1 to 5 are horizontal cross-sectional views, a verticalcross-sectional view, and a perspective view illustrating a verticalmemory device in accordance with example embodiments;

FIGS. 6 to 19 are horizontal cross-sectional views, verticalcross-sectional views, and a perspective view illustrating a method ofmanufacturing a vertical memory device in accordance with exampleembodiments; and

FIGS. 20 and 21 are a horizontal cross-sectional view and a verticalcross-sectional view illustrating a vertical memory device in accordancewith example embodiments.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which example embodiments are shown.Example embodiments may, however, be embodied in many different formsand should not be construed as limited to the example embodiments setforth herein. In the drawings, the thicknesses of layers and regions areexaggerated for clarity. Like reference numerals in the drawings denotelike elements, and thus their description will be omitted.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items. Otherwords used to describe the relationship between elements or layersshould be interpreted in a like fashion (e.g., “between” versus“directly between,” “adjacent” versus “directly adjacent,” “on” versus“directly on”).

It will be understood that, although the terms first, second, third,etc. may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. Unlessindicated otherwise, these terms are only used to distinguish oneelement, component, region, layer or section from another region, layeror section. Thus, a first element, component, region, layer or sectiondiscussed below could be termed a second element, component, region,layer or section without departing from the teachings of the exampleembodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of theexample embodiments. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, example embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to limit the scope of thepresent disclosure.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

FIGS. 1 to 5 are horizontal cross-sectional views, a verticalcross-sectional view, and a perspective view illustrating a verticalmemory device in accordance with example embodiments. Particularly, FIG.1 is a horizontal cross-sectional view illustrating arrangements ofholes and channels of the vertical memory device, FIG. 2 is a horizontalcross-sectional view illustrating arrangements of conductive patterns252 and 254 of the vertical memory device, and FIG. 3 is a horizontalcross-sectional view illustrating arrangements of bit lines 272, 274 and276 of the vertical memory device. Further, FIG. 4 is a verticalcross-sectional view cut along the line of the horizontalcross-sectional views and FIG. 5 is a perspective view illustratingmemory cells of the vertical memory device.

In all figures in this specification, a direction substantiallyperpendicular to a top surface of the substrate is referred to as afirst direction, and two directions substantially parallel to the topsurface of the substrate and substantially perpendicular to each otherare referred to as a second direction and a third direction. Further, afourth direction is substantially parallel to the top surface of thesubstrate and at an acute angle to the third direction. Additionally, adirection indicated by an arrow in the figures and a reverse directionthereto are considered as the same direction.

Referring to FIGS. 1 to 5, the vertical memory device may include aplurality of channels 170 each of which may extend in the firstdirection on a substrate 100, a charge storage structure 160 stacked onan outer sidewall of each channel 170, and a plurality of gateelectrodes 222, 224 and 226 disposed on an outer sidewall of the chargestorage structure 160. The vertical memory device may further includethe conductive patterns 252 and 254 and the bit lines 272, 274 and 276electrically connected to each channel 170.

The substrate 100 may include a semiconductor material, e.g., silicon,germanium, etc. The substrate 100 may include a first region I and asecond region II. In example embodiments, the first region I may be acell region in which vertical memory elements including the channels 170may be formed, and the second region II may be a word line cut region inwhich a third insulation layer pattern 228 may be disposed to insulatethe gate electrodes 222, 224 and 226. A plurality of first regions I anda plurality of second regions II may be disposed alternately andrepeatedly in the second direction, and each of the first regions I andthe second regions II may extend in the third direction.

Each channel 170 may extend in the first direction in the first regionI. In some example embodiments, each channel 170 may have a cup shape ofwhich a central bottom is opened. In this case, a space defined by aninner wall of each channel 170 may be filled with an insulation pattern(not shown). In other example embodiments, each channel 170 may have apillar shape. For example, each channel 170 may include doped or undopedpolysilicon or single crystalline silicon.

In example embodiments, the plurality of channels 170 may be arranged inboth of the second and third directions, and thus a plurality of channelarrays 170A, 170B and 170C may be defined. Each of the channel arrays170A, 170B and 170C may include a plurality of channel columns, and eachof the channel columns may include a plurality of channels 172A, 172B,172C, 174A, 174C, 176A, 176B and 176C which may be arranged in the thirddirection.

For example, a first channel array 170A may include a first channelcolumn, a second channel column, and a third channel column. The firstchannel column may include a plurality of first channels 172A that maybe arranged in the third direction, the second channel column mayinclude a plurality of second channels 174A that may be arranged in thethird direction, and the third channel column may include a plurality ofthird channels 176A that may be arranged in the third direction.

In example embodiments, the first channels 172A may be arranged at acentral portion of the first region I in the third direction, and thesecond channels 174A and the third channels 176A may be arranged atouter portions of the first region I in the third direction. Further,the second channels 174A may be spaced apart from the first channels172A in the fourth direction, and the third channels 176A may be spacedapart from the second channels 174A in the second direction.Accordingly, the first, second and third channels 172A, 174A and 176Amay be arranged in a zigzag pattern (that is, a staggered pattern) withrespect to the second direction, and thus more channels may be arrangedin a given area.

On the other hand, single channel array may be disposed in respectivesingle first region I. In example embodiments, three channel columns maybe disposed in the respective single first region I. As the number ofthe channel columns is limited to three, a void may not be occurredduring a process for forming a gate electrode layer.

Each of the channels 170 may be disposed in each of holes 130. As theplurality of channels 170 may constitute the channel arrays 170A, 170B,and 170C, a plurality of holes 130 may also constitute hole arrays 130A,130B, and 130C. In example embodiments, each of the hole array mayinclude three hole columns. For example, a first hole array 130A mayinclude a first hole column, a second hole column and a third holecolumn, and each of the hole columns may include a plurality of holes132A, 134A and 136A, respectively.

Referring to FIGS. 3 and 4, the charge storage structure 160 disposed onthe outer sidewall of each channel 170 may include a tunnel insulationlayer pattern 166, a charge storage layer pattern 164 and a firstblocking layer pattern 162 which may be stacked sequentially.Particularly, the tunnel insulation layer pattern 166, the chargestorage layer pattern 164 and the first blocking layer pattern 162 maysurround the outer sidewall and a bottom surface of each channel 170. Inexample embodiments, a plurality of charge storage structures 160 may bedisposed to correspond to respective channels 170.

In example embodiments, the tunnel insulation layer pattern 166 mayinclude an oxide, e.g., silicon oxide, the charge storage layer pattern164 may include a nitride, e.g., silicon nitride, and the first blockinglayer pattern 162 may include an oxide, e.g., silicon oxide.

On the other hand, a semiconductor pattern 140 making contact with thetop surface of the substrate 100 may be formed beneath each channel 170.According as the channel 170 may have the portion at a bottom thereofprotruding from the charge storage layer structure 160, thesemiconductor pattern 140 may have a concave portion at a top surfacethereof. That is, the semiconductor pattern 140 may directly contact thechannel 170 through the protrusion portion thereof. In exampleembodiments, the semiconductor pattern 140 may include doped or undopedpolysilicon, single crystalline polysilicon, doped or undopedpolygermanium or single crystalline germanium.

Additionally, a pad 180 may be formed on top surfaces of the channel 170and the charge storage layer structure 160. In example embodiments, thepad 180 may include doped or undoped polysilicon or single crystallinesilicon.

As the plurality of channels 170 may constitute the channel arrays 170A,170B, and 170C, a plurality of pads 180 may also constitute pad arrays.In example embodiments, each of the pad arrays may include three padcolumns. For example, a first pad array 180A may include a first padcolumn, a second pad column and a third pad column, and each of the padcolumns may include a plurality of pads 182A, 184A and 186A,respectively.

A plurality of first insulation patterns 115 may be formed in the firstdirection on sidewalls of the first blocking layer patterns 162,respectively. For example, each first insulation pattern 115 may includesilicon oxide. Further, a space between the first insulation layers 115at each level may be defined as a gap.

A minimum distance between the first insulation layers 115 at each levelin the first direction may be defined as a first distance T1. In exampleembodiments, the first distance T1 may be less than about 30 nm.Particularly, the first distance T1 may be in a range of about 20 nm toabout 25 nm. As the first distance T1 decrease, a total height of thevertical memory device may also decrease. Therefore, the degree ofintegration of the vertical memory device in a predetermined volume mayincrease.

The second blocking layer pattern 215 may surround a sidewall of thefirst blocking layer pattern 162 exposed by the gap, that is, maysurround an outer sidewall of the channel 170. Thus, portions of theouter sidewalls of the channels 170 may be surrounded by the secondblocking layer pattern 215. The second blocking layer pattern 215 may befurther formed on an inner wall of the gap. Top and bottom end portionsof the second blocking layer pattern 215 may extend in both of thesecond and third directions. The second blocking layer pattern 215 mayinclude, e.g., aluminum oxide and/or silicon oxide.

The plurality of gate electrodes 222, 224 and 226 may be formed on asidewall of the second blocking layer pattern 215 and may fill an innerportion of the gap. In example embodiments, the plurality of gateelectrodes 222, 224 and 226 may extend in the third direction.

The plurality of gate electrodes 222, 224 and 226 may include a groundselection line (GSL) 226, a word line 222 and a string selection line(SSL) 224 that are spaced apart from each other along the firstdirection.

Each of the GSL 226, the word line 222 and the SSL 224 may be at asingle level (e.g., one of each, each at a different height) or morethan one level, and each of the first insulation layer patterns 115 maybe interposed therebetween. In an example embodiments, the GSL 226 andthe SSL 224 may be at one level (e.g., two of each at differentheights), respectively, and the word line 222 may be at 4 levels betweenthe GSL 226 and the SSL 224. However, the GSL 226 and the SSL 224 may beat two levels, and the word line 222 may be formed at 2, 8 or 16 levels.

In example embodiments, the plurality of gate electrodes 222, 224 and226 may include, for example, a metal and/or a metal nitride. Forexample, the plurality of gate electrodes 222, 224 and 226 may include ametal and/or a metal nitride with low electrical resistance (e.g.,tungsten, tungsten nitride, titanium, titanium nitride, tantalum,tantalum nitride and/or platinum.)

The plurality of gate electrodes 222, 224 and 226 may be arranged in thesecond direction. Particularly, the plurality of gate electrodes 222,224 and 226 may be divided by a third insulation layer pattern 228.

Accordingly, the channel 170, the charge storage layer structure 160 andthe plurality of gate electrodes 222, 224 and 226 may define a gatestructure. A plurality of gate structures may be formed in the firstdirection.

Referring now to FIGS. 2 and 4, some channels of one channel array maybe electrically connected to other channels of another channel arraythrough the conductive patterns 252 and 254.

Particularly, a fourth insulation layer 230 may be formed on the firstinsulation layer pattern 115 and the pads 180. Contacts 240 may beformed through the fourth insulation layer 230, thereby contacting thepads 180. Some contacts 240 may be electrically connected to each otherthrough the first and second conductive patterns 252 and 254.

In example embodiments, a plurality of contacts 240 may be arranged inthe second direction and the third direction. Therefore, the pluralityof contacts 240 may define a plurality of contact arrays 240A, 240B and240C. Each of the contact arrays 240A, 240B and 240C may include aplurality of contact columns, and each of the contact columns mayinclude the plurality of contacts 240 arranged in the third direction.

For example, the first contact array 240A may include a first contactcolumn including a plurality of first contacts 242A, a second contactcolumn including a plurality of second contacts 244A and a third contactcolumn including a plurality of third contact 246A. Each of the first tothird contacts 242A, 244A and 246A may be electrically connected to eachof the first to third channels 172A, 174A and 176A through respectivepads 180.

The first conductive patterns 252 and the second conductive patterns 254may be disposed on the fourth insulation layer 230. The first conductivepatterns 252 and the second conductive patterns 254 may electricallyconnect the second contacts 244A, 244C with third contacts 246A, 246Band 246C. For example, the first conductive patterns 252 mayelectrically connect the second contacts 244A of the first contact array240A with the third contacts 246B of the second contact array 240B, andthe second conductive pattern 254 may electrically connect the thirdcontacts 246A of the first contact array 240A with the second contacts244C of the third contact array 240C as illustrated in FIG. 1. Further,the first contacts 242A, 242B and 242C may be electrically isolated fromthe first conductive pattern 252 and the second conductive pattern 254.

In example embodiments, a plurality of first conductive patterns 252 anda plurality of second conductive patterns 254 may be arranged in thethird direction.

Further, the first conductive pattern 252 and the second conductivepattern 254 may be curved in opposite directions. For example, a centralportion of the first conductive pattern 252 may be curved in the thirddirection, and a central portion of the second conductive pattern 254may be curved in a direction as opposed to the third direction.Therefore, the central portion of the first conductive pattern 252 maynot overlap the central portion of the second conductive pattern 254with respect to the second direction.

In example embodiments, the first conductive pattern 252 and the secondconductive pattern 254 may include a metal, a conductive metal nitride,doped polysilicon, and the like.

Referring now to FIGS. 3 and 4, the bit lines 272, 274 and 276 may beelectrically connected to the channels 170 and the pads 180 through thebit line contacts 262, 264 and 266.

In example embodiments, each of the bit lines 272, 274 and 276 mayextend in the second direction. The bit lines 272, 274 and 276 may bearranged in the third direction. Particularly, the first bit line 272,the second bit line 274 and the third bit line 276 may be arranged inthe third direction alternately and repeatedly. Further, the first tothird bit lines 272, 274 and 276 may have the same width W1, W2 and W3in the third direction, and may be spaced apart from one another by thesame distance D1.

The bit line contacts 262, 264 and 266 may be disposed through a fifthinsulation layer 260. For example, the bit line contacts 262, 264 and266 may include a metal, a conductive metal nitride, doped polysilicon,and the like.

In example embodiments, the first bit line contacts 262 may electricallyconnect the first contacts 242A, 242B and 242C with the first bit lines272. Therefore, the first bit lines 272 may be electrically connected tothe first channels 172A, 172B and 172C. The second bit lines contact 264may be electrically connected to the first conductive pattern 252 andthe second bit lines 274. Therefore, the second bit lines 274 may beelectrically connected to the second channels 174A of the first channelarray 170A and the third channels 176B of the second channel array 170B.

The third bit lines contact 266 may be electrically connected to thesecond conductive pattern 255 and the third bit lines 276. Therefore,the third bit lines 276 may be electrically connected to the thirdchannels 176A of the first channel array 170A and the second channels174B of the second channel array 170B. Accordingly, the first channel,the second channel and the third channel of one channel array may beelectrically connected to different bit lines, respectively.

The first conductive pattern 252 and the second conductive pattern 254may be curved in opposite directions, so that the second bit line 274and the third bit line 276 electrically connected to the first andsecond conductive patterns 252 and 254 respectively, may be spaced apartfrom the first bit line 272 by a predetermined distance. Accordingly,the vertical memory device may have a reduced width in the thirddirection, so that the degree of integration may increase.

According to example embodiment, the vertical memory device may includethe plurality of channels, and the plurality of channels may constitutethe channel array including three channel columns. The channels may beelectrically connected to the first to third bit lines 172 m 174 and 176through the first conductive pattern 151 or the second conductivepattern 154. The first conductive pattern 252 and the second conductivepattern 254 may be curved in opposite directions, so that the first tothird bit lines 272, 274 and 276 may be spaced apart from each other bythe predetermined distance. Therefore, the degree of integration of thevertical memory device may increase.

Moreover, as illustrated best by FIGS. 1, 4 and 5, nonvolatile memorydevices according to some embodiments of the invention can include atleast four cylindrical-shaped channel regions 170, which extendvertically from portions of a substrate 100 located at respectivevertices of at least one rhomboid when viewed in a vertical directionrelative to a surface of the substrate 100. As shown by the dotted linesin the plan view of FIG. 1, the channel regions 170 are centered atvertices of respective rhomboids (e.g., R1, R2, R3, R4 and R5; and R1′,R2′)—when viewed in a vertical direction relative to an upper surface ofthe substrate 100. In addition, a charge storage layer 160 (e.g., ONOlayer) is provided on an outer sidewall of each of thecylindrical-shaped channel regions 170. To achieve a high degree ofintegration, a plurality of vertically-stacked gate electrodes 222 areprovided, which extend adjacent each of the cylindrical-shaped channelregions 170.

FIGS. 6 to 19 are horizontal cross-sectional views, verticalcross-sectional views, and a perspective view illustrating a method ofmanufacturing a vertical memory device in accordance with exampleembodiments. The figures show methods of manufacturing the verticalmemory device of FIGS. 1 to 3, however, may not be limited thereto.

Referring to FIG. 6, a first insulation layer 110 and a sacrificiallayer 120 may be alternately and repeatedly formed on a substrate 100. Aplurality of first insulation layers 110 and a plurality of sacrificiallayers 120 may be alternately formed on each other at a plurality oflevels, respectively.

The substrate 100 may include a semiconductor material, for example,silicon and/or germanium. The substrate 100 may be divided into a firstregion I and a second region II. In example embodiments, the firstregion I and the second region II may be arranged alternately andrepeatedly in the second direction.

In example embodiments, the first insulation layer 110 and thesacrificial layer 120 may be formed by, for example, a chemical vapordeposition (CVD) process, a plasma enhanced chemical vapor deposition(PECVD) process and/or an atomic layer deposition process (ALD) process.A lowermost first insulation layer 110, which may be formed directly ona top surface of the substrate 100, may be formed by, for example, athermal oxidation process. In example embodiments, the first insulationlayer 110 may be formed to include a silicon oxide. The sacrificiallayers 120 may be formed to include, for example, a material with etchselectivity to the first insulation layer 110 (e.g., silicon nitride).

The number of the first insulation layers 110 and the number of thesacrificial layers 120 stacked on the substrate 100 may vary accordingto the desired number of a GSL 226, a word line 222 and a SSL 224 (referto FIG. 14). According to at least one example embodiments, each of theGSL 226 and the SSL 224 may be formed at a single level, and the wordline 222 may be formed at 4 levels. The sacrificial layer 120 may beformed at 6 levels, and the first insulation layer 110 may be formed at7 levels. According to at least one example embodiments, each of the GSL226 and the SSL 224 may be formed at two levels, and the word line 222may be formed at 2, 8 or 16 levels. The number of the first insulationlayers 110 and the number of the sacrificial layers 120 may varyaccording to this case. However, the number of GSLs 226, SSLs 224 andword lines 222 may not be limited herein.

Further, each of the sacrificial layers 120 may have a thicknesssubstantially the same as a first distance T1. In example embodiments,the first distance T1 may be less than about 30 nm. Particularly, thefirst distance T1 may be in a range of about 20 nm to about 25 nm. Asthe first distance T1 decrease, a total height of the vertical memorydevice may also decrease.

Referring to FIGS. 7 and 8, a plurality of holes 130 may be formedthrough the first insulation layers 110 and the sacrificial layers 120to expose a top surface of the substrate 100.

In example embodiments, after forming a hard mask on the uppermost firstinsulation layer 110, the first insulation layers 110 and thesacrificial layers 120 may be dry etched using the hard mask as an etchmask to form the holes 130. As the sacrificial layers 120 may have thethickness of the first distance T1 decrease, a total height of thevertical memory device may also decrease. Therefore, an aspect ratio ofthe holes 130 also may decrease. Accordingly, an etching process forforming the holes 130 may be performed reliability and easily.

In example embodiments, a plurality of holes 130 may arranged in thesecond direction and the third direction. Therefore, the plurality ofholes 130 may constitute hole arrays 130A, 130B and 130C. For example,the plurality of holes 130 may be arranged in a zigzag pattern withrespect to the third direction.

Each of the hole arrays 130A, 130B and 130C may include the plurality ofhole columns, and each of hole columns may include the plurality ofholes arranged in the third direction. In example embodiments, each ofthe hole arrays 130A, 130B and 130C may include three hole columns.

For example, the first hole array 130A may include a first hole columnincluding a plurality of first holes 132A, a second hole columnincluding a plurality of second holes 134A and a third hole columnincluding a plurality of third holes 136A. As illustrated in FIG. 7, thefirst holes 132A may be arranged at a central portion of the firstregion I in the third direction, and the second holes 134A and the thirdholes 136A may be arranged at outer portions of the first region I inthe third direction. Further, the second holes 134A may be spaced apartfrom the first holes 132A in the fourth direction, and the third holes136A may be spaced apart from the holes 134A in the second direction.

Referring to FIG. 9, a semiconductor pattern 140 may be formed topartially fill each hole 130, and a preliminary charge storage layerstructure 158 may be formed an inner wall of each hole 130.

Particularly, a selective epitaxial growth (SEG) process may beperformed using the exposed top surface of the substrate 100 as a seedto form the semiconductor pattern 140. Thus, the semiconductor pattern140 may be formed to include single crystalline silicon or singlecrystalline germanium according to the material of the substrate 100,and in some cases, impurities may be doped thereinto. Alternatively, anamorphous silicon layer may be formed to fill the holes 130, and a laserepitaxial growth (LEG) process or a solid phase epitaxial (SPE) processmay be performed on the amorphous silicon layer to form thesemiconductor pattern 140. In example embodiments, the semiconductorpattern 140 may be formed to have a top surface higher than that of thesacrificial layer 120, in which the GSL 226 (See FIG. 14) may be formedsubsequently.

Then, a first blocking layer, a charge storage layer and a tunnelinsulation layer may be sequentially formed on an inner wall of theholes 130, a top surface of the semiconductor pattern 140, and a topsurface of the hard mask. The first blocking layer, the charge storagelayer and the tunnel insulation layer may constitute the preliminarycharge storage layer structure 158.

In example embodiments, the first blocking layer may be formed toinclude an oxide, e.g., silicon oxide, the charge storage layer may beformed to include a nitride, e.g., silicon nitride, and the tunnelinsulation layer may be formed to include an oxide, e.g., silicon oxide.

As the holes 130 has a reduced aspect ratio, the first blocking layer,the charge storage layer and the tunnel insulation layer may be formedon the inner wall of the holes 130 conformally.

Referring to FIGS. 10 and 11, channels 170, second insulation layerpatterns 175 and pads 180 may be formed to fill the holes 130.

Particularly, a bottom surface of the preliminary charge storage layerstructure 158 and an upper portion of the semiconductor pattern 140 maybe partially removed to form a first recess. A channel layer and asecond insulation layer may be formed to sufficiently fill the firstrecess and a remaining portion of each hole 130, and then upper portionsof the preliminary charge storage layer structure 158, the channel layerand the second insulation layer on the top surface of the uppermostfirst insulation layer 110 may be removed to form the charge storagelayer structure 160, the channels 170 and the second insulation layerpatterns 175. Therefore, the charge storage layer structure 160 mayinclude a first blocking layer pattern 162, a charge storage layerpattern 164 and a tunnel insulation layer pattern 166.

In example embodiments, a plurality of channels may constitute channelarrays. For example, a first channel array 170A may include a firstchannel column including a plurality of first channels 172A, a secondchannel column including a plurality of second channels 174A, and athird channel column including a plurality of third channels 176A.

Then, upper portions of the first blocking layer pattern 162, the chargestorage layer pattern 164, the tunnel insulation layer pattern 166, thechannels 170 and the second insulation layer patterns 172 may bepartially removed to form a second recess, and the pad 180 may be formedto fill the second recess. For example, the pad 180 may include a metal,a conductive metal nitride, doped polysilicon, and the like.

In example embodiments, a plurality of pads may constitute pad arrays.For example, a first pad array 180A may include a first pad columnincluding a plurality of first pads 182A, a second pad column includinga plurality of second pads 184A, and a third pad column including aplurality of third pads 186A.

Referring to FIGS. 12 and 13, a first opening 190 may be formed throughthe first insulation layers 110 and the sacrificial layers 120 to exposea top surface of the substrate 100, and then the sacrificial layer 120may be removed to form a gap 200 between the first insulation layerpatterns 115 at adjacent levels.

In example embodiments, after forming a hard mask (not shown) on theuppermost first insulation layer 110, the insulation layers 110 and thesacrificial layers 120 may be, for example, dry etched using the hardmask as an etch mask to form the first opening 190. The first opening190 may extend in the first direction.

In this case, the first opening 190 may have a width substantially thesame as a second distance T2 in the second direction. In exampleembodiments, the second distance T2 may be less than about 80 nm.Particularly, the second distance T2 may be in a range of about 65 nm toabout 75 nm. That is, as the second distance T2 decrease, the degree ofintegration of the vertical memory device may increase.

As the first opening 190 may be formed, the first insulation layer 110may be transformed into a first insulation layer pattern 115. Aplurality of first insulation layer patterns 115 may be formed in thesecond direction at each level, and each first insulation layer pattern115 may extend in the third direction.

Then, the sacrificial layer 120 may be removed by a wet etching process.Particularly, the sacrificial layer 120 exposed by the first opening 190may be removed by a wet etching process using phosphoric acid orsulfuric acid as a etching solution. Therefore, portions of the outersidewall of the first blocking layer pattern 162 may be exposed by thegap 200. The gap 200 may have a width substantially the same as thefirst distance T1 in the first direction.

Referring to FIG. 14, a second blocking layer 210 and a gate electrodelayer 220 may be formed on the exposed portion of the outer sidewall ofthe blocking layer pattern 162, the exposed portion of the sidewall ofthe semiconductor pattern 140, an inner sidewall of the gap 200, asurface of the first insulation pattern 115, the exposed top surface ofthe substrate 100 and top surfaces of the pad 180.

The second blocking layer 210 may be formed using an insulation materialsuch as aluminum oxide or silicon oxide. In an example embodiment, thesecond blocking layer 210 may be formed by a sequentially flowdeposition (SFD) process or an atomic layer deposition ALD) process.

The gate electrode layer 220 may be formed to include a metal of a lowresistance, e.g., tungsten, titanium, tantalum, platinum, and the like.When the gate electrode layer 220 is formed to include tungsten, thegate electrode layer 220 may be formed by a CVD process or an SFDprocess using tungsten hexafluoride (WF6) as a source gas.

As mentioned above, three channel columns may be disposed in therespective single first region I, and the plurality of channels may bearranged in the zigzag pattern, so that the width of the first region Iin the second direction may decrease. Therefore, the second blockinglayer 210 and the gate electrode layer 220 may be conformally formed.When performing a deposition process for forming the gate electrodelayer 220, the source gas molecules may easily move into the gap 200through the first opening 190. Therefore, a void may not be formed inthe gate electrode layer 220.

Further, the width of the gap 200 in the first direction may be lessthan about 30 nm, so that the gate electrode layer 220 may have areduced thickness which may be limited to the width of the gap 200. Eventhough, the first opening 190 may have the width of about 65 nm to about75 nm in the second direction, the upper portion of the first opening190 may not be blocked by the gate electrode layer 220.

Referring to FIG. 11, the second blocking layer 210 the gate electrodelayer 220 may be partially removed to form a plurality of gateelectrodes 222, 224 and 226, and then a third insulation layer pattern228 may be formed to fill the first opening 190.

In example embodiments, the gate electrode layer 210 may be partiallyremoved by, for example, a wet etch process. In example embodiments, theplurality of gate electrodes 222, 224 and 226 may fill the gap 200. Theplurality of gate electrodes 222, 224 and 226 may be formed to extend inthe third direction.

The plurality of gate electrodes 222, 224 and 226 may include a GSL 226,the word line 222 and the SSL 224 sequentially located from a topsurface of the substrate 100. Each of the GSL 226, the word line 222 andthe SSL 224 may be formed at a single level or at a plurality of levels.According to at least one example embodiment, each of the GSL 226 andthe SSL 224 may be formed at single level, and the word line 222 may beformed at 4 levels between the GSL 226 and the SSL 224. However, thenumber of GSLs 226, word lines 222 and SSLs 224 may not be limitedthereto. The GSL 226 may be formed adjacent to the semiconductor pattern140, the word line 222 and the SSL 224 may be formed adjacent to thechannels 170.

In a process for partially removing the gate electrode layer 220, thesecond blocking layer 210 may be partially removed, the first opening190 exposing a top surface of the substrate 100 and extending in thethird direction may be formed again, and impurities may be implantedinto the exposed top surface of the substrate 100 to form an impurityregion 105.

In example embodiments, the impurities may include n-type impurities,for example, phosphorus and/or arsenic. In example embodiments, theimpurity region 105 may extend in the third direction and serve as acommon source line (CSL).

Then, the third insulation layer pattern 228 may be formed to fill thefirst opening 190. In example embodiments, after filling the firstopening 190 with a third insulating interlayer, the third insulatinginterlayer may be planarized until a top surface of the uppermost firstinsulation layer pattern 115 may be exposed to form the third insulationlayer pattern 228.

In other example embodiments, a bottom surface of the first opening 190may be lower than a top surface of the substrate 100. Then, the impurityregion 105 may be formed by a SEG process.

Referring to FIGS. 16 and 17, a fourth insulation layer 230 may beformed on the first and third insulation layer patterns 115 and 228 andthe pads 180, contacts 240 may be formed through the fourth insulationlayer 230, and then conductive patterns 252 and 254 may be formed on thefourth insulation layer 230 and the contacts 240.

In example embodiments, a plurality of contacts 240 may be arranged inthe second direction and the third direction. Therefore, the pluralityof contacts 240 may define a plurality of contact arrays 240A, 240B and240C. Each of the contact arrays 240A, 240B and 240C may include aplurality of contact columns, and each of the contact columns mayinclude the plurality of contacts 240 arranged in the third direction.The arrangement of the contacts 240 may be substantially the same asthose illustrated in FIG. 2.

For example, the first contact array 240A may include a first contactcolumn including a plurality of first contacts 242A, a second contactcolumn including a plurality of second contacts 244A and a third contactcolumn including a plurality of third contact 246A. Each of the first tothird contacts 242A, 244A and 246A may be electrically connected to eachof the first to third channels 172A, 174A and 176A through respectivepads 180.

Then, a conductive layer may be formed on the fourth insulation layer230 and the contacts 240, and the conductive layer may be partiallyremoved to form the first conductive pattern 252 and the secondconductive pattern 254. The first conductive patterns 252 and the secondconductive patterns 254 may electrically connect the second contacts244A, 244C with third contacts 246A, 246B and 246C. For example, thefirst conductive patterns 252 may electrically connect the secondcontacts 244A of the first contact array 240A with the third contacts246B of the second contact array 240B, and the second conductive pattern254 may electrically connect the third contacts 246A of the firstcontact array 240A with the second contacts 244C of the third contactarray 240C as illustrated in FIG. 1. Further, the first contacts 242A,242B and 242C may be electrically isolated from the first conductivepattern 252 and the second conductive pattern 254.

In example embodiments, a plurality of first conductive patterns 252 anda plurality of second conductive patterns 254 may be arranged in thethird direction.

Further, the first conductive pattern 252 and the second conductivepattern 254 may be curved in opposite directions. For example, a centralportion of the first conductive pattern 252 may be curved in the thirddirection, and a central portion of the second conductive pattern 254may be curved in a direction as opposed to the third direction.Therefore, the central portion of the first conductive pattern 252 maynot overlap the central portion of the second conductive pattern 254with respect to the second direction.

Referring to FIGS. 18 and 19, a fifth insulation layer 260 may be formedon the fourth insulation layer 230 to cover the conductive patterns 252and 254 and the contacts 242A, bit line contacts 262, 264 and 266 may beformed through the fifth insulation layer 260, and then bit lines 272,274 and 276 may be formed on the fifth insulation layer 260 and the bitline contacts 262, 264 and 266.

In example embodiments, a plurality of the bit line contacts 262, 264and 266 may be arranged in the second direction and the third direction.In this case, first bit line contacts 262 may be electrically connectedto the first contacts 242A, 242B and 242C, the second bit line contacts264 may be electrically connected to the first conductive pattern 252,and the third bit line contacts 266 may be electrically connected to thesecond conductive pattern 254. In an example embodiment, the second andthe third bit line contacts 264 and 266 may directly contact the centralportions of the first and second conductive patterns 252 and 254.

Then, a bit line layer may be formed on the fifth insulation layer 260,and then the bit line layer may be patterned to form the bit lines 272,274 and 276. In example embodiments, each of the bit lines 272, 274 and276 may extend in the second direction. The bit lines 272, 274 and 276may be arranged in the third direction. Particularly, the first bit line272, the second bit line 274 and the third bit line 276 may be arrangedin the third direction alternately and repeatedly.

The first to third bit lines 272, 274 and 276 may be electricallyconnected to the first to third bit line contacts 262, 264 and 266,respectively. Therefore, the first channel, the second channel and thethird channel of one channel array may be electrically connected todifferent bit lines, respectively.

Further, the first to third bit lines 272, 274 and 276 may have the samewidth W1, W2 and W3 in the third direction, and may be spaced apart fromone another by the same distance D1. The first conductive pattern 252and the second conductive pattern 254 may be curved in oppositedirections, so that the first to third bit lines 272, 274 and 276 may bespaced apart from each other by the predetermined distance. Therefore,the degree of integration of the vertical memory device may increase.

FIGS. 20 and 21 are a horizontal cross-sectional view and a verticalcross-sectional view illustrating a vertical memory device in accordancewith example embodiments.

FIG. 20 is a horizontal cross-sectional view illustrating arrangementsof holes and channel of the vertical memory device, and FIG. 21 is avertical cross-sectional view cut along the line of the horizontalcross-sectional view. The vertical memory device may be substantiallythe same as or similar to the vertical memory device described withreference to FIGS. 1 to 5 except for an arrangement of channels and bitlines.

Referring to FIGS. 20 and 21, the vertical memory device may include aplurality of channels 17Q each of which may extend in the firstdirection on a substrate 100, a charge storage structure 160 stacked onan outer sidewall of each channel 170, and a plurality of gateelectrodes 222, 224 and 224 disposed on an outer sidewall of the chargestorage structure 160. The vertical memory device may further includethe bit lines 273, 275 and 277 electrically connected to each channel170.

The substrate 100 may include a first region I and a second region II.In example embodiments, the first region I may be a cell region in whichvertical memory elements including the channels 170 may be formed.

A plurality of channels 170, a plurality of holes and a plurality ofpads 180 may be disposed in the first region I of the substrate 100. Inexample embodiments, the plurality of channels 170, the plurality ofholes and the plurality of pads 180 may constitute channel arrays, holearrays and pad arrays 180A, 180B, 180C, respectively. Further, singlechannel array may be disposed in respective single first region I. Inexample embodiments, three channel columns may be disposed in therespective single first region I.

Referring now to FIG. 20, the bit lines 273, 275 and 277 may beelectrically connected to the channels 170 through the bit line contacts263, 265 and 267.

In example embodiments, each of the bit lines 273, 275 and 277 mayextend in a fifth direction oblique to the second direction. The bitlines 273, 275 and 277 may be arranged in the third direction.Particularly, the first bit line 273, the second bit line 275 and thethird bit line 277 may be arranged in the third direction alternatelyand repeatedly. Further, the first to third bit lines 273, 275 and 277may have the same width W1, W2 and W3 in the third direction, and may bespaced apart from one another by the same distance D1.

As the bit lines 273, 275 and 277 may extend in the fifth direction, thefirst channel, the second channel and the third channel of one channelarray may be electrically connected to different bit lines,respectively.

The foregoing is illustrative of at least one example embodiment and isnot to be construed as limiting thereof. Although a few exampleembodiments have been described, those skilled in the art will readilyappreciate that many modifications are possible in the exampleembodiments without materially departing from the novel teachings andadvantages of the present inventive concept. Accordingly, all suchmodifications are intended to be included within the scope of thepresent inventive concept as defined in the claims. In the claims,means-plus-function clauses are intended to cover the structuresdescribed herein as performing the recited function and not onlystructural equivalents but also equivalent structures. Therefore, it isto be understood that the foregoing is illustrative of various exampleembodiments and is not to be construed as limited to the specificexample embodiments disclosed, and that modifications to the disclosedexample embodiments, as well as other example embodiments, are intendedto be included within the scope of the appended claims.

What is claimed is:
 1. A nonvolatile memory device, comprising: at leastfour cylindrical-shaped channel regions extending vertically fromportions of a substrate located at respective vertices of at least onerhomboid when viewed in a vertical direction relative to a surface ofthe substrate; a charge storage layer on an outer sidewall of each ofsaid at least four cylindrical-shaped channel regions; a plurality ofvertically-stacked gate electrodes extending adjacent each of said atleast four cylindrical-shaped channel regions; and a plurality of bitlines extending over said at least four cylindrical-shaped channelregions, said plurality of bit lines including at least first, secondand third bit lines electrically coupled to respective ones of said atleast four cylindrical-shaped channel regions; and wherein the first,second and third bit lines extend parallel to each other and in adirection oblique relative to all sides of the at least one rhomboidwhen viewed in the vertical direction.
 2. The memory device of claim 1,wherein said at least four cylindrical-shaped channel regions comprisesseven cylindrical-shaped channel regions positioned at respectivevertices of two rhomboids that share a common vertex when viewed in avertical direction relative to the surface of the substrate.
 3. Thememory device of claim 1, wherein said at least four cylindrical-shapedchannel regions comprises five cylindrical-shaped channel regionspositioned at respective vertices of two rhomboids that share threecommon vertices when viewed in a vertical direction relative to thesurface of the substrate.
 4. The memory device of claim 1, wherein saidat least four cylindrical-shaped channel regions comprises sevencylindrical-shaped channel regions positioned at respective vertices offour rhomboids that share a common vertex when viewed in a verticaldirection relative to the surface of the substrate.
 5. The memory deviceof claim 4, wherein one of the seven cylindrical-shaped channel regionsis located at a vertex that is shared by each of the four rhomboids. 6.A vertical memory device, comprising: a plurality of channel arraysincluding a plurality of channels in a first region on a substrate, eachof the channels extending in a first direction substantiallyperpendicular to a top surface of the substrate; a charge storage layerstructure including a tunnel insulation layer pattern, a charge storagelayer pattern and a blocking layer pattern which are sequentiallystacked on a sidewall of each channel in a second directionsubstantially parallel to the top surface of the substrate; and aplurality of gate electrodes arranged on a sidewall of the chargestorage layer structure and spaced apart from each other in the firstdirection; wherein each channel array includes: a first channel columnincluding a plurality of first channels disposed at a central portion ofthe first region with respect to a third direction substantiallyperpendicular to the first direction and the second direction; a secondchannel column including a plurality of second channels disposed at anouter portion of the first region, the second channels being spacedapart from respective first channels in a fourth direction oblique tothe third direction; and a third channel column including a plurality ofthird channels disposed at the outer portion of the first region, thethird channels being spaced apart from respective second channels in thesecond direction; a first conductive pattern electrically connecting asecond channel of one channel array with a third channel of anotherchannel array; and a second conductive pattern electrically connecting athird channel of the one channel array with a second channel of theother channel array; wherein a plurality of first conductive patterns isarranged in the third direction, and a plurality of second conductivepatterns is arranged in the third direction; wherein a central portionof the first conductive pattern is curved in the third direction, and acentral portion of the second conductive pattern is curved in adirection opposed to the third direction.
 7. The vertical memory deviceof claim 6, wherein the first channels, the second channels and thethird channels are arranged in a zigzag pattern with respect to thethird direction.
 8. The vertical memory device of claim 6, wherein theplurality of channel arrays include a first channel array, a secondchannel array spaced apart from the first channel array in a directionopposed to the second direction, and a third channel array spaced apartfrom the first channel array in the second direction.
 9. The verticalmemory device of claim 8, wherein the first conductive patternelectrically connects the second channel of the first channel array withthe third channel of the second channel array, and the second conductivepattern electrically connects the third channel of the first channelarray with the second channel of the third channel array.
 10. Thevertical memory device of claim 6, wherein the central portion of thefirst conductive pattern does not overlap the central portion of thesecond conductive pattern with respect to the second direction.
 11. Avertical memory device, comprising: a plurality of channel arraysincluding a plurality of channels in a first region on a substrate, eachof the channels extending in a first direction substantiallyperpendicular to a top surface of the substrate; a charge storage layerstructure including a tunnel insulation layer pattern, a charge storagelayer pattern and a blocking layer pattern which are sequentiallystacked on a sidewall of each channel in a second directionsubstantially parallel to the top surface of the substrate; and aplurality of gate electrodes arranged on a sidewall of the chargestorage layer structure and spaced apart from each other in the firstdirection; wherein each channel array includes: a first channel columnincluding a plurality of first channels disposed at a central portion ofthe first region with respect to a third direction substantiallyperpendicular to the first direction and the second direction; a secondchannel column including a plurality of second channels disposed at anouter portion of the first region, the second channels being spacedapart from respective first channels in a fourth direction oblique tothe third direction; and a third channel column including a plurality ofthird channels disposed at the outer portion of the first region, thethird channels being spaced apart from respective second channels in thesecond direction; a first conductive pattern electrically connecting asecond channel of one channel array with a third channel of anotherchannel array; a second conductive pattern electrically connecting athird channel of the one channel array with a second channel of theother channel array; and a plurality of first bit line, a plurality ofsecond bit line and a plurality of third bit line electrically connectedto respective channels; wherein the first bit lines are electricallyconnected to the first channels, the second bit lines are electricallyconnected to the second channels or the third channels through the firstconductive patterns, and the third bit lines are electrically connectedto the second channels or the third channels through the secondconductive patterns; wherein the first bit lines overlap centralportions of the first channels with respect to the first direction, thesecond bit lines overlap central portions of the first conductivepatterns with respect to the first direction, and the third bit linesoverlap central portions of the second conductive patterns with respectto the first direction.
 12. The vertical memory device of claim 11,wherein the first bit lines, the second bit lines and the third bitlines extend in the second direction, and the first bit lines, thesecond bit lines and the third bit lines are arranged alternately andrepeatedly in the third direction.